(Not Applicable)
(Not Applicable)
The present invention relates generally to integrated circuit chip package technology, and more particularly to a unique lead frame design for a micro lead frame (MLF) package wherein a special plated half-etched feature is included in the lead frame design which increases the solderable area of the leads of the lead frame to a printed circuit board, thus creating stronger final solder joints with increased second level reliability.
Integrated circuit dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the integrated circuit die and an underlying substrate such as a printed circuit board (PCB) or motherboard. The elements of such a package include a metal lead frame, an integrated circuit die, bonding material to attach the integrated circuit die to the lead frame, bond wires which electrically connect pads on the integrated circuit die to individual leads of the lead frame, and a hard plastic encapsulant material which covers the other components and forms the exterior of the package.
The lead frame is the central supporting structure of such a package. A portion of the lead frame is internal to the package, i.e., completely surrounded by the plastic encapsulant. Portions of the leads of the lead frame extend externally from the package or are partially exposed within the encapsulant material for use in electrically connecting the chip package to another component. In certain chip packages, a portion of the die pad of the lead frame also remains exposed within the exterior of the package for use as a heat sink.
For purposes of high-volume, low-cost production of chip packages, a current industry practice is to etch or stamp a thin sheet of metal material to form a panel or strip which defines multiple lead frames. A single strip may be formed to include multiple arrays, with each such array including a multiplicity of lead frames in a particular pattern. In a typical chip package manufacturing process, the integrated circuit dies are mounted and wire bonded to respective ones of the lead frames, with the encapsulant material then being applied to the strip so as to encapsulate the integrated circuit dies, bond wires, and portions of each of the lead frames in the above-described manner.
Upon the hardening of the encapsulant material, the lead frames within the strip are cut apart or singulated for purposes of producing the individual chip packages. Such singulation is typically accomplished via a saw singulation process. In this process, a saw blade is advanced along xe2x80x9csaw streetsxe2x80x9d which extend in prescribed patterns between the lead frames as required to facilitate the separation of the lead frames from each other in the required manner.
As indicated above, in certain current MLF package designs, the bottom surface of each of the leads of the lead frame is exposed within the bottom surface of the package body formed by the hardening of the encapsulant material, with one end surface of each of the leads being exposed within a corresponding peripheral or side surface of the package body. In this design, solderable surfaces are provided on only the bottom surface of the package body, and more particularly, by the exposed bottom surfaces of the leads. The MLF package is attached to the printed circuit board or motherboard by printing solder paste on the board, positioning the exposed bottom surfaces of the leads upon the solder paste, and completing a hot reflow process. However, the limited solderable area on the MLF package and resultant decreased solder joint strength gives rise to reliability problems concerning the potential failure of one or more of the solder joints between the MLF package and the motherboard. Previous attempts to increase solder joint life were to optimize or increase the size of the leads, the material set, and the board design. However, material sets which give the best package level performance may also produce the worst board level performance, thus necessitating another option to increase overall solder strength and reliability between the MLF package and the motherboard.
The present invention addresses the solder joint reliability issue by providing a lead frame design wherein those surfaces of the leads exposed within the bottom and side surfaces of the package body are plated and configured in a manner allowing solder to reflow up the lead ends, thereby increasing the overall solder joint strength and reliability between the MLF package and motherboard. In this regard, the plated lead ends increase the solderable area of the leads of the MLF package to the motherboard, with the final solder joint being stronger with increased second level reliability.
The uniquely configured lead ends may be formed as a half-etched feature in the lead frame design. This half-etched design has the effect of increasing saw efficiency in the saw singulation process due to the resultant reduction of copper or other metal in the saw streets. The half-etched design further reduces the cut line interface between the saw and each of the leads, thus reducing the amount of burring which typically occurs upon the leads as a result of the saw singulation process. Saw generated burrs at the seating plan of each lead in the lead frame adversely affect solder mounting and joint reliability. In current MLF package fabrication methodologies, lead burrs are controlled by limiting the feed rate of the saw along the saw streets and by using specifically developed, high cost saw blades. The reduced burring attributable to the half-etched design of the lead ends increases output and allows for the use of lower cost saw blades.
As indicated above, as a result of forming the half-etched plated ends of the leads, metal material is removed from the saw streets, thus reducing the area of each of the leads susceptible to burring. This plated, half-etched feature in the present lead frame design becomes an integral part of the finished lead connection of the MLF package. The uniquely configured, plated ends of the leads of the lead frame constructed in accordance in accordance with the present invention may alternatively be formed through the implementation of a two-pass saw process, though such process does not provide the same saw cut efficiency and reduced burring attributes of the half-etched design. The half-etched or sawed leads can be incorporated into standard lead frame designs at no additional cost, and provide higher board-level (solder joint) reliability and improved lead dimensional stability. In the case of the half-etched leads, further advantages include the improvement of the saw singulation process (increased saw cut efficiency), and reduced burring on the saw cut leads as indicated above.
In accordance with the present invention, there is provided a lead frame which comprises a frame defining a central opening. Disposed within the central opening is a die pad which is connected to the frame. Also connected to the frame are a plurality of leads which extend within the opening toward the die pad. Each of the leads defines opposed top and bottom surfaces, an inner end, an outer end, and an opposed pair of side surfaces. The bottom surface and the outer end collectively define a corner region of the lead. Formed within the corner region is a recess. The recesses facilitate the reflow of solder up the lead ends, thereby increasing the overall solder joint strength and reliability between the semiconductor package incorporating the lead frame and an underlying substrate such as a printed circuit board or motherboard. The surfaces of the lead defining the recess are plated, with the inclusion of the recess within each lead effectively increasing the solderable area of the leads of the semiconductor package to the printed circuit board, with the final solder joint being stronger with increased second level reliability.
The recesses within the leads may be formed as a half-etched feature in the lead frame design. This half-etched design has the effect of increasing saw efficiency in the saw singulation process due to the resultant reduction of copper or other metal material in the saw streets. The half-etched design further reduces the cut line interface between the saw and each of the leads, thus reducing the amount of burring which typically occurs upon the leads as a result of the saw singulation process.
Further in accordance with the present invention, there is provided a modified inboard design for a semiconductor package which is adapted to facilitate an increase in second level solder joint reliability by creating solder fillets upon those portions of the bottom surfaces of the leads which are exposed within the bottom surface of the package body. More particularly, the solder fillets are created by forming copper bumps upon the exposed bottom surfaces of each of the leads, the copper bumps facilitating the creation of solder fillets. Each of the copper bumps may optionally include a solder plate formed thereon.